1. Field of the Invention
The invention disclosed herein relates generally to the device configuration of power MOSFETs. More particularly, this invention relates to a novel and improved device structure for preventing shoot through problem by using a capacitor formed on top of the gate as a second poly with an inter-poly dielectric layer.
2. Description of the Prior Art
Conventional power MOSFET devices still face the shoot through problems that result in excessive dissipation and efficiency loss. Referring to FIG. 1 for a circuit diagram of a conventional buck converter 10 that includes a high side MOSFET 15 and a low side MOSFET 20 serially connected between an input terminal 25 having an input voltage represented by Vin and a ground terminal 30. The drain of the low side MOSFET 20 is connected to the source of the high side MOSFET 15 at a mid point 35 connecting to the load 40 through inductance L and capacitance C. When the buck converter 10 operates at high speed, a shoot through condition becomes a problem when both the high side and low side MOSFET are turned on at the same time causing a shoot through current to flow between the input terminal 25 and the ground terminal 30. The shoot through condition results in excessive dissipation and efficiency loss. In order to avoid the shoot through problem, a controlling circuit 45 is implemented to control the gate signals to generate a dead time between the gate signals for the high side and low side MOSFET. FIG. 2 shows such a dead time between the time when the high side MOSFET 15 is turned off and the time when the low side MOSFET 20 is turned on such that the high side and low side MOSFETs are prevented from turning on simultaneously.
However, the shoot through problem cannot be completely avoided due to the fact that a large drain current is generated at the low side MOSFET 20 when the high side MOSFET 15 is turned on as shown in FIG. 3 due to a large rate of change of the voltage, i.e., dV/dt, at the mid-connection point 35. FIG. 4 shows an equivalent circuit of the buck converter wherein the drain current generated flows through the gate-drain capacitor Cgd and then to the ground through the internal gate-source capacitor Cgs or through an equivalent circuit segment comprises gate resistor Rg inductor Lg, and external gate drive resistance Rext. Under such circumstances, if the impedance from the gate to the ground is not below a certain value then the drain current, i.e., Cdg*dV/dt, will generate a voltage drop across the gate of the low side MOSFET that would be large enough to turn on the low side MOSFET 20 thus inducing shoot-through. The peak of the spike voltage can be expressed as:Vspike=Vin*Crss/(Crss+Ciss)Where the input capacitance Ciss and feedback capacitance Crss are determined by the following equations:Ciss=Cgd+Cgs Crss=CgdIn modern circuit designs, a designer typically controls the problem by using a large gate-source capacitance Cgs or a low Crss/Ciss ratio. Increasing Cgs results in Crss/Ciss reduction. As it is shown in FIG. 4, a large Cgs has the benefit of drawing most of the transient drain current Cdg*dV/dt to the ground through the capacitor, leaving less current to go through the external gate controller thus lowering the gate spike voltage and avoiding shoot through. Alternately, the problem may also be prevented by providing a low gate resistance and using a high current gate drive with low Rext. However, if the gate drive circuitry, i.e., the control circuit 45, is remote from the MOSFET, the inductance Lg may become quite large. This causes the current path connected with Rg, Rext, and Lg to have great impedance thus leaving only the Cgs path to sink the transient current. The only way to suppress the shoot through current is by increasing the capacitance Cgs to reduce the impedance. However, this solution will lead to excessive gate charge losses in the low side MOSFET 20. For the above reasons, a person of ordinary skill of the art is faced with limitations and difficulties in designing a converter to effectively prevent the shoot through problem.
FIG. 5A shows a typical conventional trench MOSFET. As illustrated in this trench MOSFET cell, input capacitance Ciss includes the source to gate capacitance Cgs and the body to gate capacitance and Crss is the gate to drain capacitance. The ratio Crss/Ciss can be reduced either by increasing Ciss or reduce Crss. As shown in FIG. 5B, Crss is determined by the vertical area capacitance of the trench beyond the body region shown as C1, and C2 and further determined by another horizontal area capacitance shown as C3. Reducing the area capacitance C1, C2, or C3 can reduce the capacitance Crss. However, due to the process control, yield requirements and minimum linewidth limitations in the fabrication the trenched MOSFET, it is difficult to reduce the capacitances C1, C2, or C3. FIG. 6 shows a MOSFET with increased source depth to increase Ciss. This technique is difficult to implement for several reasons. First of all, the source junction depth may have to be significantly increased in order to increase the Ciss for reducing the Crss/Ciss ratio. However, in order to maintain the same channel length, the body junction depth must also be increased. The configuration as shown in FIG. 6 is not practical useful due to the limitations that it is difficult to manufacture a reliable trenched MOSFET device with short channel when implemented with a deep source and deep body junction.
Therefore, a need still exists in the art to provide an improved device configuration and manufacturing methods to make MOSFET devices with a reduced Crss/Ciss ratio to prevent the occurrences of shoot-through and resolve the above discussed difficulties as now encountered in the prior art.